// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  sdmam_common_regs_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:19:00 Create file
// ******************************************************************************

#ifndef __SDMAM_COMMON_REGS_REG_OFFSET_FIELD_H__
#define __SDMAM_COMMON_REGS_REG_OFFSET_FIELD_H__

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT0_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT0_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT1_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT1_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT2_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT2_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT3_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT3_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT4_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT4_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT5_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT5_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT6_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT6_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT7_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT7_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT8_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT8_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT9_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT9_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT10_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT10_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT11_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT11_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT12_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT12_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT13_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT13_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT14_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT14_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT15_LEN    16
#define SDMAM_COMMON_REGS_DFX_EMU_PRESS_CNT15_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF0_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF0_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF1_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF1_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF2_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF2_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF3_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF3_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF4_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF4_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF5_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF5_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF6_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF6_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF7_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF7_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_ATS_DST_OSTD_NUM_LEN      5
#define SDMAM_COMMON_REGS_DFX_ATS_DST_OSTD_NUM_OFFSET   21
#define SDMAM_COMMON_REGS_DFX_ATS_REQ_DST_REMAIN_LEN    21
#define SDMAM_COMMON_REGS_DFX_ATS_REQ_DST_REMAIN_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_TXBUF_BUSY_LEN            1
#define SDMAM_COMMON_REGS_DFX_TXBUF_BUSY_OFFSET         26
#define SDMAM_COMMON_REGS_DFX_ATS_SRC_OSTD_NUM_LEN      5
#define SDMAM_COMMON_REGS_DFX_ATS_SRC_OSTD_NUM_OFFSET   21
#define SDMAM_COMMON_REGS_DFX_ATS_REQ_SRC_REMAIN_LEN    21
#define SDMAM_COMMON_REGS_DFX_ATS_REQ_SRC_REMAIN_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_ATS_REQ_OSTD_TYPE_LEN    16
#define SDMAM_COMMON_REGS_DFX_ATS_REQ_OSTD_TYPE_OFFSET 16
#define SDMAM_COMMON_REGS_DFX_ATS_REQ_OSTD_VEC_LEN     16
#define SDMAM_COMMON_REGS_DFX_ATS_REQ_OSTD_VEC_OFFSET  0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF11_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF11_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_TXBUF_SRC_VA_SEND_L_LEN    16
#define SDMAM_COMMON_REGS_DFX_TXBUF_SRC_VA_SEND_L_OFFSET 16
#define SDMAM_COMMON_REGS_DFX_TXBUF_DST_VA_SEND_H_LEN    16
#define SDMAM_COMMON_REGS_DFX_TXBUF_DST_VA_SEND_H_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF13_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF13_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF14_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF14_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF15_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF15_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF16_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF16_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF17_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF17_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_ICDTDATA_PAYLOAD_LEN    32
#define SDMAM_COMMON_REGS_DFX_ICDTDATA_PAYLOAD_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF19_LEN         24
#define SDMAM_COMMON_REGS_DFX_PROBE_INF19_OFFSET      8
#define SDMAM_COMMON_REGS_DFX_ICDT_PENDING_LEN        1
#define SDMAM_COMMON_REGS_DFX_ICDT_PENDING_OFFSET     7
#define SDMAM_COMMON_REGS_DFX_ICDTVALID_LEN           1
#define SDMAM_COMMON_REGS_DFX_ICDTVALID_OFFSET        6
#define SDMAM_COMMON_REGS_DFX_ICDT_READY_LEN          1
#define SDMAM_COMMON_REGS_DFX_ICDT_READY_OFFSET       5
#define SDMAM_COMMON_REGS_DFX_ICDT_LAST_LEN           1
#define SDMAM_COMMON_REGS_DFX_ICDT_LAST_OFFSET        4
#define SDMAM_COMMON_REGS_DFX_ICDTDATA_PAYLOAD2_LEN    4
#define SDMAM_COMMON_REGS_DFX_ICDTDATA_PAYLOAD2_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF20_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF20_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF21_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF21_OFFSET 0

#define SDMAM_COMMON_REGS_INT_NS_INT_CONVERGE_LEN    16
#define SDMAM_COMMON_REGS_INT_NS_INT_CONVERGE_OFFSET 16
#define SDMAM_COMMON_REGS_INT_S_INT_CONVERGE_LEN     16
#define SDMAM_COMMON_REGS_INT_S_INT_CONVERGE_OFFSET  0

#define SDMAM_COMMON_REGS_SUBSQE_INNER_CNT_L_LEN    12
#define SDMAM_COMMON_REGS_SUBSQE_INNER_CNT_L_OFFSET 20
#define SDMAM_COMMON_REGS_SUBSQE_OUTER_CNT_LEN      17
#define SDMAM_COMMON_REGS_SUBSQE_OUTER_CNT_OFFSET   3
#define SDMAM_COMMON_REGS_SUBSQE_PENDING_CNT_LEN    3
#define SDMAM_COMMON_REGS_SUBSQE_PENDING_CNT_OFFSET 0

#define SDMAM_COMMON_REGS_TLBI_ICCT_CNT_UNCOMP_LEN         4
#define SDMAM_COMMON_REGS_TLBI_ICCT_CNT_UNCOMP_OFFSET      28
#define SDMAM_COMMON_REGS_WAITING_ATS_DONE_LEN             1
#define SDMAM_COMMON_REGS_WAITING_ATS_DONE_OFFSET          27
#define SDMAM_COMMON_REGS_TLBI_CLR_TXNID_FIFO_LEN          1
#define SDMAM_COMMON_REGS_TLBI_CLR_TXNID_FIFO_OFFSET       26
#define SDMAM_COMMON_REGS_TLBI_WAIT_LAST_WR_CQE_LEN        1
#define SDMAM_COMMON_REGS_TLBI_WAIT_LAST_WR_CQE_OFFSET     25
#define SDMAM_COMMON_REGS_TLBI_WAITING_SRC_ATS_RSP_LEN     1
#define SDMAM_COMMON_REGS_TLBI_WAITING_SRC_ATS_RSP_OFFSET  24
#define SDMAM_COMMON_REGS_TLBI_WAITING_DEST_ATS_RSP_LEN    1
#define SDMAM_COMMON_REGS_TLBI_WAITING_DEST_ATS_RSP_OFFSET 23
#define SDMAM_COMMON_REGS_TLBI_MATCH_LEN                   1
#define SDMAM_COMMON_REGS_TLBI_MATCH_OFFSET                22
#define SDMAM_COMMON_REGS_TLBI_LAST_MATCH_LEN              1
#define SDMAM_COMMON_REGS_TLBI_LAST_MATCH_OFFSET           21
#define SDMAM_COMMON_REGS_TLBI_MATCH_ASID_SRC_LEN          1
#define SDMAM_COMMON_REGS_TLBI_MATCH_ASID_SRC_OFFSET       20
#define SDMAM_COMMON_REGS_TLBI_MATCH_VMID_SRC_LEN          1
#define SDMAM_COMMON_REGS_TLBI_MATCH_VMID_SRC_OFFSET       19
#define SDMAM_COMMON_REGS_TLBI_MATCH_SID_SRC_LEN           1
#define SDMAM_COMMON_REGS_TLBI_MATCH_SID_SRC_OFFSET        18
#define SDMAM_COMMON_REGS_TLBI_MATCH_SSID_SRC_LEN          1
#define SDMAM_COMMON_REGS_TLBI_MATCH_SSID_SRC_OFFSET       17
#define SDMAM_COMMON_REGS_TLBI_MATCH_VA_SRC_LEN            1
#define SDMAM_COMMON_REGS_TLBI_MATCH_VA_SRC_OFFSET         16
#define SDMAM_COMMON_REGS_TLBI_MATCH_VA_RNG_SRC_LEN        1
#define SDMAM_COMMON_REGS_TLBI_MATCH_VA_RNG_SRC_OFFSET     15
#define SDMAM_COMMON_REGS_TLBI_MATCH_EL_SRC_LEN            1
#define SDMAM_COMMON_REGS_TLBI_MATCH_EL_SRC_OFFSET         14
#define SDMAM_COMMON_REGS_TLBI_MATCH_ASID_DST_LEN          1
#define SDMAM_COMMON_REGS_TLBI_MATCH_ASID_DST_OFFSET       13
#define SDMAM_COMMON_REGS_TLBI_MATCH_VMID_DST_LEN          1
#define SDMAM_COMMON_REGS_TLBI_MATCH_VMID_DST_OFFSET       12
#define SDMAM_COMMON_REGS_TLBI_MATCH_SID_DST_LEN           1
#define SDMAM_COMMON_REGS_TLBI_MATCH_SID_DST_OFFSET        11
#define SDMAM_COMMON_REGS_TLBI_MATCH_SSID_DST_LEN          1
#define SDMAM_COMMON_REGS_TLBI_MATCH_SSID_DST_OFFSET       10
#define SDMAM_COMMON_REGS_TLBI_MATCH_VA_DST_LEN            1
#define SDMAM_COMMON_REGS_TLBI_MATCH_VA_DST_OFFSET         9
#define SDMAM_COMMON_REGS_TLBI_MATCH_VA_RNG_DST_LEN        1
#define SDMAM_COMMON_REGS_TLBI_MATCH_VA_RNG_DST_OFFSET     8
#define SDMAM_COMMON_REGS_TLBI_MATCH_EL_DST_LEN            1
#define SDMAM_COMMON_REGS_TLBI_MATCH_EL_DST_OFFSET         7
#define SDMAM_COMMON_REGS_TLBI_MATCH_SEC_LEN               1
#define SDMAM_COMMON_REGS_TLBI_MATCH_SEC_OFFSET            6
#define SDMAM_COMMON_REGS_SUBSQE_BUSY_LEN                  1
#define SDMAM_COMMON_REGS_SUBSQE_BUSY_OFFSET               5
#define SDMAM_COMMON_REGS_SUBSQE_INNER_CNT_H_LEN           5
#define SDMAM_COMMON_REGS_SUBSQE_INNER_CNT_H_OFFSET        0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF26_LEN      28
#define SDMAM_COMMON_REGS_DFX_PROBE_INF26_OFFSET   4
#define SDMAM_COMMON_REGS_TLBI_ACT_PENDING_LEN     1
#define SDMAM_COMMON_REGS_TLBI_ACT_PENDING_OFFSET  3
#define SDMAM_COMMON_REGS_TLBI_LAST_PENDING_LEN    1
#define SDMAM_COMMON_REGS_TLBI_LAST_PENDING_OFFSET 2
#define SDMAM_COMMON_REGS_TLBI_MATCH_BOTH_LEN      1
#define SDMAM_COMMON_REGS_TLBI_MATCH_BOTH_OFFSET   1
#define SDMAM_COMMON_REGS_TLBI_ICCT_PENDING_LEN    1
#define SDMAM_COMMON_REGS_TLBI_ICCT_PENDING_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF27_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF27_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF28_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF28_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF29_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF29_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF30_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF30_OFFSET 0

#define SDMAM_COMMON_REGS_DFX_PROBE_INF31_LEN    32
#define SDMAM_COMMON_REGS_DFX_PROBE_INF31_OFFSET 0



#define SDMAM_COMMON_REGS_SMMU_FAULT_EVENT_CNT_LEN    16
#define SDMAM_COMMON_REGS_SMMU_FAULT_EVENT_CNT_OFFSET 16
#define SDMAM_COMMON_REGS_SMMU_RESUME_CNT_LEN         16
#define SDMAM_COMMON_REGS_SMMU_RESUME_CNT_OFFSET      0

#define SDMAM_COMMON_REGS_LAST_FAULT_TERMINATE_LEN    1
#define SDMAM_COMMON_REGS_LAST_FAULT_TERMINATE_OFFSET 10
#define SDMAM_COMMON_REGS_LAST_FAULT_STALL_LEN        1
#define SDMAM_COMMON_REGS_LAST_FAULT_STALL_OFFSET     9
#define SDMAM_COMMON_REGS_LAST_FAULT_REPORT_LEN       1
#define SDMAM_COMMON_REGS_LAST_FAULT_REPORT_OFFSET    8
#define SDMAM_COMMON_REGS_LAST_FAULT_TYPE_LEN         8
#define SDMAM_COMMON_REGS_LAST_FAULT_TYPE_OFFSET      0

#define SDMAM_COMMON_REGS_INT_NS_MASK_LEN    1
#define SDMAM_COMMON_REGS_INT_NS_MASK_OFFSET 0

#define SDMAM_COMMON_REGS_INT_IOE_S_MASK_LEN    1
#define SDMAM_COMMON_REGS_INT_IOE_S_MASK_OFFSET 2
#define SDMAM_COMMON_REGS_INT_IOC_S_MASK_LEN    1
#define SDMAM_COMMON_REGS_INT_IOC_S_MASK_OFFSET 1
#define SDMAM_COMMON_REGS_INT_S_MASK_LEN        1
#define SDMAM_COMMON_REGS_INT_S_MASK_OFFSET     0

#define SDMAM_COMMON_REGS_SDMAM_IOE_STATUS_LEN    8
#define SDMAM_COMMON_REGS_SDMAM_IOE_STATUS_OFFSET 0



#define SDMAM_COMMON_REGS_SDMAM_IOC_STATUS_LEN    8
#define SDMAM_COMMON_REGS_SDMAM_IOC_STATUS_OFFSET 0



#define SDMAM_COMMON_REGS_INT_GROUP0_SEL_LEN    8
#define SDMAM_COMMON_REGS_INT_GROUP0_SEL_OFFSET 0



#define SDMAM_COMMON_REGS_INT_GROUP1_SEL_LEN    8
#define SDMAM_COMMON_REGS_INT_GROUP1_SEL_OFFSET 0



#define SDMAM_COMMON_REGS_INT_GROUP2_SEL_LEN    8
#define SDMAM_COMMON_REGS_INT_GROUP2_SEL_OFFSET 0



#define SDMAM_COMMON_REGS_INT_GROUP3_SEL_LEN    8
#define SDMAM_COMMON_REGS_INT_GROUP3_SEL_OFFSET 0



#define SDMAM_COMMON_REGS_TSELW_LEN    2
#define SDMAM_COMMON_REGS_TSELW_OFFSET 5
#define SDMAM_COMMON_REGS_TSELR_LEN    2
#define SDMAM_COMMON_REGS_TSELR_OFFSET 3
#define SDMAM_COMMON_REGS_TEST_LEN     3
#define SDMAM_COMMON_REGS_TEST_OFFSET  0

#define SDMAM_COMMON_REGS_ECC_INJECT_SECU_EN_LEN     1
#define SDMAM_COMMON_REGS_ECC_INJECT_SECU_EN_OFFSET  18
#define SDMAM_COMMON_REGS_ECC_INJECT_2BIT_SEL_LEN    8
#define SDMAM_COMMON_REGS_ECC_INJECT_2BIT_SEL_OFFSET 10
#define SDMAM_COMMON_REGS_ECC_INJECT_2BIT_EN_LEN     1
#define SDMAM_COMMON_REGS_ECC_INJECT_2BIT_EN_OFFSET  9
#define SDMAM_COMMON_REGS_ECC_INJECT_1BIT_SEL_LEN    8
#define SDMAM_COMMON_REGS_ECC_INJECT_1BIT_SEL_OFFSET 1
#define SDMAM_COMMON_REGS_ECC_INJECT_1BIT_EN_LEN     1
#define SDMAM_COMMON_REGS_ECC_INJECT_1BIT_EN_OFFSET  0

#define SDMAM_COMMON_REGS_REG_SP_ARB_TIMEOUT_LIMIT_LEN    4
#define SDMAM_COMMON_REGS_REG_SP_ARB_TIMEOUT_LIMIT_OFFSET 0

#define SDMAM_COMMON_REGS_MPAM_ID_VF_EN_LEN          1
#define SDMAM_COMMON_REGS_MPAM_ID_VF_EN_OFFSET       16
#define SDMAM_COMMON_REGS_MPAM_ID_REPLACE_EN_LEN     1
#define SDMAM_COMMON_REGS_MPAM_ID_REPLACE_EN_OFFSET  15
#define SDMAM_COMMON_REGS_REPLACE_QOS_LEN            4
#define SDMAM_COMMON_REGS_REPLACE_QOS_OFFSET         11
#define SDMAM_COMMON_REGS_REPLACE_MPAM_PARTID_LEN    8
#define SDMAM_COMMON_REGS_REPLACE_MPAM_PARTID_OFFSET 3
#define SDMAM_COMMON_REGS_REPLACE_MPAM_PMG_LEN       2
#define SDMAM_COMMON_REGS_REPLACE_MPAM_PMG_OFFSET    1
#define SDMAM_COMMON_REGS_REPLACE_MPAM_NS_LEN        1
#define SDMAM_COMMON_REGS_REPLACE_MPAM_NS_OFFSET     0

#define SDMAM_COMMON_REGS_DIRECT_SQE_BAL_LEN    32
#define SDMAM_COMMON_REGS_DIRECT_SQE_BAL_OFFSET 0

#define SDMAM_COMMON_REGS_DIRECT_SQE_BAH_LEN    16
#define SDMAM_COMMON_REGS_DIRECT_SQE_BAH_OFFSET 0

#define SDMAM_COMMON_REGS_ARWUSER_SAFETY_LEVEL_CHK_LEN    3
#define SDMAM_COMMON_REGS_ARWUSER_SAFETY_LEVEL_CHK_OFFSET 13
#define SDMAM_COMMON_REGS_ARWUSER_SAFETY_LEVEL_LEN        3
#define SDMAM_COMMON_REGS_ARWUSER_SAFETY_LEVEL_OFFSET     10
#define SDMAM_COMMON_REGS_ARWUSER_CSP_LEN                 1
#define SDMAM_COMMON_REGS_ARWUSER_CSP_OFFSET              9
#define SDMAM_COMMON_REGS_ARWUSER_SEQ_TYPE_LEN            2
#define SDMAM_COMMON_REGS_ARWUSER_SEQ_TYPE_OFFSET         7
#define SDMAM_COMMON_REGS_ARWUSER_NIDV_LEN                1
#define SDMAM_COMMON_REGS_ARWUSER_NIDV_OFFSET             6
#define SDMAM_COMMON_REGS_ARWUSER_LPIDV_LEN               1
#define SDMAM_COMMON_REGS_ARWUSER_LPIDV_OFFSET            5
#define SDMAM_COMMON_REGS_ARWUSER_SNOOPABLE_LEN           1
#define SDMAM_COMMON_REGS_ARWUSER_SNOOPABLE_OFFSET        4
#define SDMAM_COMMON_REGS_ARWUSER_SOID_LEN                3
#define SDMAM_COMMON_REGS_ARWUSER_SOID_OFFSET             1
#define SDMAM_COMMON_REGS_ARWUSER_SO_LEN                  1
#define SDMAM_COMMON_REGS_ARWUSER_SO_OFFSET               0

#define SDMAM_COMMON_REGS_ARWUSER_LPID_LEN         13
#define SDMAM_COMMON_REGS_ARWUSER_LPID_OFFSET      19
#define SDMAM_COMMON_REGS_ARWUSER_STASH_LEN        1
#define SDMAM_COMMON_REGS_ARWUSER_STASH_OFFSET     18
#define SDMAM_COMMON_REGS_ARWUSER_PMG_LEN          2
#define SDMAM_COMMON_REGS_ARWUSER_PMG_OFFSET       16
#define SDMAM_COMMON_REGS_DMAM2TBU_CMD_TYPE_LEN    3
#define SDMAM_COMMON_REGS_DMAM2TBU_CMD_TYPE_OFFSET 13
#define SDMAM_COMMON_REGS_ARWUSER_TYPE_LEN         4
#define SDMAM_COMMON_REGS_ARWUSER_TYPE_OFFSET      9
#define SDMAM_COMMON_REGS_ARWUSER_THPORT_LEN       2
#define SDMAM_COMMON_REGS_ARWUSER_THPORT_OFFSET    7
#define SDMAM_COMMON_REGS_ARWUSER_TH_LEN           1
#define SDMAM_COMMON_REGS_ARWUSER_TH_OFFSET        6
#define SDMAM_COMMON_REGS_ARWUSER_NS_LEN           1
#define SDMAM_COMMON_REGS_ARWUSER_NS_OFFSET        5
#define SDMAM_COMMON_REGS_ARWUSER_NO_LEN           1
#define SDMAM_COMMON_REGS_ARWUSER_NO_OFFSET        4
#define SDMAM_COMMON_REGS_ARWUSER_FP_LEN           1
#define SDMAM_COMMON_REGS_ARWUSER_FP_OFFSET        3
#define SDMAM_COMMON_REGS_ARWUSER_RINVLD_LEN       1
#define SDMAM_COMMON_REGS_ARWUSER_RINVLD_OFFSET    2
#define SDMAM_COMMON_REGS_ARWUSER_FNA_LEN          1
#define SDMAM_COMMON_REGS_ARWUSER_FNA_OFFSET       1
#define SDMAM_COMMON_REGS_ARWUSER_FA_LEN           1
#define SDMAM_COMMON_REGS_ARWUSER_FA_OFFSET        0

#define SDMAM_COMMON_REGS_DFX_ERR_REC_DIS_LEN      8
#define SDMAM_COMMON_REGS_DFX_ERR_REC_DIS_OFFSET   12
#define SDMAM_COMMON_REGS_DFX_PROBE_CHL_SEL_LEN    6
#define SDMAM_COMMON_REGS_DFX_PROBE_CHL_SEL_OFFSET 6
#define SDMAM_COMMON_REGS_DFX_SPBUF_SEL_LEN        6
#define SDMAM_COMMON_REGS_DFX_SPBUF_SEL_OFFSET     0

#define SDMAM_COMMON_REGS_RESUME_TOUT_TH_LEN    20
#define SDMAM_COMMON_REGS_RESUME_TOUT_TH_OFFSET 0

#define SDMAM_COMMON_REGS_INT_TOUT_TH_LEN    20
#define SDMAM_COMMON_REGS_INT_TOUT_TH_OFFSET 0

#define SDMAM_COMMON_REGS_AXUSER_BIT0TO31_LEN    32
#define SDMAM_COMMON_REGS_AXUSER_BIT0TO31_OFFSET 0

#define SDMAM_COMMON_REGS_AXUSER_BIT49TO63_LEN    15
#define SDMAM_COMMON_REGS_AXUSER_BIT49TO63_OFFSET 17
#define SDMAM_COMMON_REGS_AXUSER_CMD_TYPE_LEN     3
#define SDMAM_COMMON_REGS_AXUSER_CMD_TYPE_OFFSET  14
#define SDMAM_COMMON_REGS_AXUSER_BIT39TO45_LEN    7
#define SDMAM_COMMON_REGS_AXUSER_BIT39TO45_OFFSET 7
#define SDMAM_COMMON_REGS_AXUSER_NS_LEN           1
#define SDMAM_COMMON_REGS_AXUSER_NS_OFFSET        6
#define SDMAM_COMMON_REGS_AXUSER_BIT32TO37_LEN    6
#define SDMAM_COMMON_REGS_AXUSER_BIT32TO37_OFFSET 0

#define SDMAM_COMMON_REGS_AXUSER_BIT64TO95_LEN    32
#define SDMAM_COMMON_REGS_AXUSER_BIT64TO95_OFFSET 0

#define SDMAM_COMMON_REGS_ATS_REQ_PROT_DAT_INST_LEN     1
#define SDMAM_COMMON_REGS_ATS_REQ_PROT_DAT_INST_OFFSET  10
#define SDMAM_COMMON_REGS_ATS_REQ_PROT_NS_LEN           1
#define SDMAM_COMMON_REGS_ATS_REQ_PROT_NS_OFFSET        9
#define SDMAM_COMMON_REGS_ATS_REQ_PROT_PRIVILEGE_LEN    1
#define SDMAM_COMMON_REGS_ATS_REQ_PROT_PRIVILEGE_OFFSET 8
#define SDMAM_COMMON_REGS_AXUSER_BIT96TO103_LEN         8
#define SDMAM_COMMON_REGS_AXUSER_BIT96TO103_OFFSET      0

#define SDMAM_COMMON_REGS_SNAP_EN_LEN       1
#define SDMAM_COMMON_REGS_SNAP_EN_OFFSET    1
#define SDMAM_COMMON_REGS_CNT_CLR_CE_LEN    1
#define SDMAM_COMMON_REGS_CNT_CLR_CE_OFFSET 0

#define SDMAM_COMMON_REGS_CH_MOVE_LENGTH_CNT_CLR_LEN    1
#define SDMAM_COMMON_REGS_CH_MOVE_LENGTH_CNT_CLR_OFFSET 0

#define SDMAM_COMMON_REGS_TLBI_FLAG_EN_LEN                1
#define SDMAM_COMMON_REGS_TLBI_FLAG_EN_OFFSET             25
#define SDMAM_COMMON_REGS_TLBI_MATCH_ASID_EN_LEN          1
#define SDMAM_COMMON_REGS_TLBI_MATCH_ASID_EN_OFFSET       24
#define SDMAM_COMMON_REGS_TLBI_MATCH_NS_EN_LEN            1
#define SDMAM_COMMON_REGS_TLBI_MATCH_NS_EN_OFFSET         23
#define SDMAM_COMMON_REGS_TLBI_MATCH_EL_EN_LEN            1
#define SDMAM_COMMON_REGS_TLBI_MATCH_EL_EN_OFFSET         22
#define SDMAM_COMMON_REGS_BRESP_ERR_REPORT_EN_LEN         1
#define SDMAM_COMMON_REGS_BRESP_ERR_REPORT_EN_OFFSET      21
#define SDMAM_COMMON_REGS_ICDT_TOTAL_OTSD_LEN             7
#define SDMAM_COMMON_REGS_ICDT_TOTAL_OTSD_OFFSET          14
#define SDMAM_COMMON_REGS_SP_PRIO_ARB_LEN                 1
#define SDMAM_COMMON_REGS_SP_PRIO_ARB_OFFSET              13
#define SDMAM_COMMON_REGS_QOS_ARB_EN_LEN                  1
#define SDMAM_COMMON_REGS_QOS_ARB_EN_OFFSET               12
#define SDMAM_COMMON_REGS_TRANSLATE_ICG_EN_LEN            1
#define SDMAM_COMMON_REGS_TRANSLATE_ICG_EN_OFFSET         11
#define SDMAM_COMMON_REGS_SDMAA_NUM_LEN                   4
#define SDMAM_COMMON_REGS_SDMAA_NUM_OFFSET                7
#define SDMAM_COMMON_REGS_CH_INT_GROUP_CONVERGE_EN_LEN    1
#define SDMAM_COMMON_REGS_CH_INT_GROUP_CONVERGE_EN_OFFSET 6
#define SDMAM_COMMON_REGS_CH_INT_CONVERGE_EN_LEN          1
#define SDMAM_COMMON_REGS_CH_INT_CONVERGE_EN_OFFSET       5
#define SDMAM_COMMON_REGS_SMMU_DVM_SYNC_EN_LEN            1
#define SDMAM_COMMON_REGS_SMMU_DVM_SYNC_EN_OFFSET         3
#define SDMAM_COMMON_REGS_CQ_TIMEOUT_REPORT_INT_EN_LEN    1
#define SDMAM_COMMON_REGS_CQ_TIMEOUT_REPORT_INT_EN_OFFSET 2
#define SDMAM_COMMON_REGS_SAFETY_CHECK_EN_LEN             1
#define SDMAM_COMMON_REGS_SAFETY_CHECK_EN_OFFSET          1
#define SDMAM_COMMON_REGS_SMMU_DVM_FAST_EN_LEN            1
#define SDMAM_COMMON_REGS_SMMU_DVM_FAST_EN_OFFSET         0

#endif // __SDMAM_COMMON_REGS_REG_OFFSET_FIELD_H__
